1. Field of the Invention
The present invention relates to an electron beam lithographic process, more particularly, to an electrically conductive layer-providing composition suitable for forming an electron beam resist pattern in an electron beam lithographic process, and a process for the formation of resist patterns using the electrically conductive layer-providing composition. The present invention can be advantageously utilized in the production of semiconductor devices such as large-scale integrated (LSI) circuits, very-large-scale integrated (VLSI) circuits, and bubble memory devices.
2. Description of the Related Art
Currently, in view of the high degree of density and integration required for elements in the production of LSIs, VLSIs and other semiconductor devices, an electron beam (EB) lithographic process in which an electron beam is used as an exposure source, is now widely used in place of other conventional radiation processes such as ultraviolet radiation, X-rays and ion beams, and a plurality of resist materials suitable for this EB lithographic process, such as a silicon-containing resist are used. In this EB lithographic process, a surface of the resist layer is sequentially scanned with an electron beam in accordance with a predetermined pattern of images to be recorded. Unfortunately, during the EB scanning or patterning, a site to be newly scanned is adversely affected by an electrical charge accumulated in the exposed sites adjacent thereto. Namely, since the exposed site has been electrically charged by the EB process, an electrical field created thereby has an affect on the course of the scanning beam directed to an adjacent new site. More particularly, the scanning beam is affected by the electrical field and is distorted, and thus an exposure pattern of the beam recorded as a latent image in the resist layer is misaligned. FIGS. 1A and 1B illustrate this formation of the shifted resist pattern; wherein FIG. 1A is a plane view of the semiconductor device having an EB resist pattern formed on a substrate thereof. In FIG. 1A, a substrate 1 has two circuit elements 3 and 4 having fabricated thereon and a pattern 2 of the EB resist to be used as a mask in the next fabrication step. The hatched area shows an unmasked surface of the substrate surface. The illustrated EB resist pattern will be produced if electrification of the resist layer does not occur during the EB scanning, but as described above, in practice, this electrification of the resist layer is unavoidable, and therefore, as illustrated in FIG. 1B, a misaligned pattern 5 of the resist is produced on the surface of substrate 1. Apparently, the semiconductor device material having a misaligned resist pattern must be discarded to avoid a production of commercially unacceptable devices, and further lowers the yield and increases the production costs. Therefore, there is an urgent need for an improved EB lithographic process not having the above-described problem of a misalignment of the exposure pattern.
Numerous patent publications teach that the above problem can be solved by using an electrically conductive layer or coating, as such a layer or coating will effectively discharge or dissipate any electrical charge accumulated in the resist layer. Further, these publications teach that such an electrically conductive layer can be formed by any conventional film formation methods, including, for example, a vacuum deposition of metals or electrically conductive inorganic materials, or a coating of a polymeric material containing metals, electrically conductive inorganic materials, surface-active agents, charge transfer agents or complexes, or related materials dispersed therein. Typical of the patent publications teaching the above technologies are those shown as follows:
(1) Japanese Unexamined Patent Publication (Kokai) No. 54-43681
This Kokai concerns an EB exposure method, and teaches the use of a carbon thin film through which electrons accumulated on an EB resist film are discharged. After the EB patterning is completed, the carbon layer is removed by methyl isobutyl ketone, which is a developer for the EB resist film.
(2) Japanese Kokai No. 54-116883
This Kokai concerns an EB exposure method, and teaches the vacuum deposition of a conductive film such as aluminum on an EB resist film, to improve the exposure accuracy by avoiding the usual electrostatic accumulation occurring during the EB process. The conductive film is removed by using a 0.1N NaOH solution.
(3) Japanese Kokai No. 56-114323
This Kokai concerns an EB lithographic method, and teaches immersion of a substrate, having an EB resist film deposited thereon, in a solution of metal chloride or complex salt, to thereby impart a conductivity to the resist film, whereby the aforementioned electric charging is prevented.
(4) Japanese Kokai No. 56-125833
This Kokai concerns an EB exposure methods, and teaches the use of an EB resist containing conductive fine powders such as carbon dispersed therein on an insulating material. When the EB is pattern-scanned on the resist film, a very accurate resist pattern can be formed, because the electrification of the resist film and warping of the EB pattern are prevented.
(5) Japanese Kokai No. 56-125834
This Kokai concerns an EB exposure method, and teaches an insertion of a conductive glass film between an EB resist film and an insulating material, to prevent an electrification of the EB resist film during the EB exposure.
(6) Japanese Kokai No. 58-54633
This Kokai concerns a microfabrication method whereby, to reduce fogging caused by a back scattering of the EB, a high-density conductive film such as a vacuum deposited Pt layer is inserted between an EB resist layer and a fabricated underlying layer.
(7) Japanese Kokai No. 58-136029
This Kokai concerns a pattern formation process preventing an electrification under exposure to the EB and teaches the use of an intermediate layer consisting of a chalcogenide glass in a three-layered resist structure (i.e., an organic polymer layer, the intermediate layer and an EB resist layer).
(8) Japanese Kokai No. 59-93441
This Kokai concerns an EB resist material having a low volume resistivity (10.sup.0 -10.sup.10 .OMEGA.cm) low enough to prevent electrification during the EB exposure, and teaches an addition of halogen-tetracyanoethylene to a charge transfer type compound such as perylene halide.
(9) Japanese Kokai 59-104126
This Kokai concerns a patterning method using a four-layered resist structure (i.e., a resin resist layer, a layer of an inorganic material, a conductive layer and an EB resist layer). The conductive layer is formed by sputtering molybdenum at a thickness of about 0.01 .mu.m on a silicon oxide layer as the inorganic layer. The presence of the conductive layer effectively prevents a misalignment of the EB pattern.
(10) Japanese Kokai No. 59-132124
This Kokai concerns a production process for semiconductor devices whereby, to prevent electrification of an EB resist layer during the EB exposure, a conductive polysilicon layer is inserted between the EB resist layer and an insulating layer.
(11) Japanese Kokai No. 63-181428
This Kokai concerns a process for the formation of resist patterns in a multilayer resist process whereby, to prevent electrification of an EB resist layer, a conductive layer such as a thin film of polyvinyl alcohol doped with minute particles of carbon is inserted between the EB resist layer and a silicon substrate.
(12) Japanese Kokai No. 63-204724
This Kokai concerns a process for the formation of resist patterns in a multilayer resist process whereby, to prevent a lower resist layer from electrification without using an Si thin film, a polymeric thin film comprising a salt of an anion radical of polystyrene sulfonic acid and a positively charged radical such as a layer of ammonium polystyrene sulfonate, is coated on a silicon substrate.
(13) Japanese Kokai No. 63-254728
This Kokai concerns a process for the formation of EB resist patterns whereby, to obtain a resist pattern having an accurate pattern, an ammonium polystyrene sulfonate film as an EB resist layer is formed on a semi-insulating GaAs substrate.
(14) Japanese Kokai No. 63-254729
This Kokai concerns a process for the formation of EB resist patterns whereby, to obtain a resist pattern without distortion, a thin conductive film of ammonium polystyrene sulfonate and an EB resist film of polymethylmethacrylate are formed on a semi-insulating GaAs substrate.
Note, among these Japanese Kokais, Japanese Kokai Nos. 63-254728 and 63-254729 were published in Japan after the filing data (Oct. 13, 1988) of the basic Japanese application of the present application, and are cited herein only for reference.
Nevertheless, problems arise in the formation of the conductive layer suggested in each of these Japanese Kokais, since a vacuum deposition or sputtering method requires a specific device and thus, it is preferable to avoid the use of such a method and to further simplify the formation process. Further, when the polymeric material having a conductive material such as metal or conductive inorganic materials dispersed therein is used in the formation of the conductive layer, the resultant layer suffers from an insufficient layer formation and poor properties of the layer. For example, small particles of the dispersed conductive material can remain on a surface of the resist layer and hinder the formation of an accurate and fine resist pattern. Furthermore, when the surface-active agents or charge transfer agents are used as the conductive material, a remarkable reduction of the antistatic function thereof occurs, because the antistatic function is notably reduced by various factors such as aging or environmental conditions, for example, temperature and humidity. Obviously, the prior art conductive layers for use in the EB lithographic process face serious problems in the operability of the process, formability of the layer and storage stability.